PreviousElectronics and Communication Engineering / Digital Electronics - Sequential Circuits
2026 Q49
A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the X...
NextElectronics and Communication Engineering / Digital Electronics - Sequential Circuits
2023 Q63
In a given sequential circuit, initial states are Q1 = 1 and Q2 = 0. For a clock frequency of 1 MHz, the frequency of signal Q2 in kHz, is ________ (rounded off to the nearest inte...