flip-flop

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input P0 is set to logic '0' and P1 is set to logic '1' at all times. Th...

In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2...

The sequence of states (Q1Q0) of the given synchronous sequential circuit is

The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are

In a given sequential circuit, initial states are Q1 = 1 and Q2 = 0. For a clock frequency of 1 MHz, the frequency of signal Q2 in kHz, is ________ (rounded off to the nearest inte...

In the circuit shown, the clock frequency, i.e., the frequency of the Clk signal, is 12 kHz. The frequency of the signal at Q_2 is _________ kHz.

The state transition diagram for the circuit shown is

A master slave flip-flop has the characteristic that

A new clocked "X-Y" flip-flop is defined with two inputs, X and Y in addition to the clock input. The flip-flop functions as follows: If XY=00, the flip-flop changes stage with eac...