GATE Electronics & Communication

A 10-bit analog-to-digital converter (ADC) has a sampling frequency of 1 MHz and a full scale voltage of 3.3 V . For an input sinusoidal signal with frequency 500 kHz , the maximum...

A 3-input majority logic gate has inputs $X, Y$ and $Z$. The output $F$ of the gate is logic ' 1 ' if two or more of the inputs are logic ' 1 '. The output $F$ is logic ' 0 ' if tw...

For the Boolean function $F(A, B, C, D) = \sum m(0,2,5,7,8,10,12,13,14,15)$, the essential prime implicants are _________.

A machine has a 32-bit architecture with 1-word long instructions. It has 24 registers and supports an instruction set of size 40. Each instruction has five distinct fields, namely...

In a number system of base $r$, the equation $x^2 - 12x + 37 = 0$ has $x = 8$ as one of its solutions. The value of $r$ is _______.

A 4-bit priority encoder has inputs $D_3, D_2, D_1,$ and $D_0$ in descending order of priority. The two-bit output $AB$ is generated as 00, 01, 10, and 11 corresponding to inputs $...

A full scale sinusoidal signal is applied to a 10-bit ADC. The fundamental signal component in the ADC output has a normalized power of 1 W, and the total noise and distortion norm...

The signal-to-noise ratio (SNR) of an ADC with a full-scale sinusoidal input is given to be 61.96 dB. The resolution of the ADC is __________ bits (rounded off to the nearest integ...

Select the Boolean function(s) equivalent to x + yz, where x, y, and z are Boolean variables, and + denotes logical OR operation.

Select the correct statement(s) regarding CMOS implementation of NOT gates.

Consider a Boolean gate (D) where the output Y is related to the inputs A and b as, Y = A + $$\overline B $$, where + denotes logical OR operation. The Boolean inputs '0' and '1' a...

A digital transmission system uses a $(7,4)$ systematic linear Hamming code for transmitting data over a noisy channel. If three of the message-code word pairs in this code ( $m_i...

Addressing of a $32 K \times 16$ memory is realized using a single decoder. The minimum number of AND gates required for the decoder is :

An 8-bit unipolar (all analog output values are positive) digital-to-analog converter (DAC) has a full-scale voltage range from 0 V to 7.68 V . If the digital input code is 1001011...

A 10 bit D/A converter is calibrated over the full range 0 to 10 V . If the input to the D/A converter is 13 A (in hex), the output (rounded off to three decimal places) is $\_\_\_...

$P, Q$ and $R$ are the decimal integers corresponding to the 4-bit binary number 1100 considered in signed magnitude, 1 's complement and 2 's complement representation, respective...

A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each cycle, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds and the RED is tur...

A function F(A, B, C) defined by three Boolean variables A, B and C when expressed as sum of products is given by F = $$\overline A .\overline B .\overline C + \overline A .B.\over...

Which one of the following gives the simplified sum of products expression for the Boolean function $$F = {m_0} + {m_2} + {m_3} + {m_5},$$ where $$F = {m_0} + {m_2} + {m_3} + {m_5}...

In a DRAM,

The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is

The Boolean expression F(X, Y, Z)= $$\overline X Y\overline Z + X\overline {Y\,} \overline Z + XY\overline Z + XYZ$$ converted into the canonical product of sum (POS)from is

Consider a four bit D to A converter. The analog value corresponding to digital signals of values 0000 and 0001 are 0 V and 0.0625 V respectively. The analog value (in Volts ) corr...

A 16 Kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines neede...

A function of Boolean variables X,Y and Z is expressed in terms of the min-terms as F(X, Y, Z)=$$\sum\limits_{}^{} {} $$m(1,2,5,6,7) Which one of the product of sums given below is...

A 3-input majority gate is defined by the logic function M (a,b,c) = ab+bc+ca. Which one of the following gates is represented by the function M$$\left( {\overline {M\left( {a,b,c}...

The number of bytes required to represent the decimal number 1856357 in packed BCD (Binary Coded Decimal) form is __________ .

The Boolean expression (X+Y)(X+$$\overline Y $$)+($$\overline {(X\overline Y ) + \overline X } $$ simplifies to

If X and Y are inputs and the Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the following diagrams implements a half-subtractor?

For an n - variable Boolean function maximum number of prime implicants is

Consider the Boolean function, F(w,z,y,z)=wy+ xy +$$\overline w \,xyz + \overline w \,\overline x y\, + xz + \,\overline {x\,} \,\overline y \,$$ $$\overline z $$ Which one of the...

If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in

In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (N = X - Y) are given by

In the sum of products function f (x,y,z) = $$\sum {} $$m (2,3,4,5), the prime implicants are

A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one o...

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is

Two D flip-flops are connected as a synchronous counter that goes through the following Q B Q A sequence $$00 \to 11 \to 01 \to 10 \to 00 \to ......$$

What are the minimum number of 2-to 1 multiplexers required to generate a 2-input AND gate and a 2-input EX-OR gate?

If X=1 in the logic equation $$\left[ {X + Z\left\{ {\overline Y + (\overline Z + X\overline {Y)} } \right\}} \right]$$ $$\left\{ {\overline X + \overline Z (X + Y)} \right\} = 1,$...

The full forms of the abbreviations TTL and COMS in reference to logic families are

X = 01110 and Y = 11001 are two 5-bit binary numbers represented in two’s complement format. The sum of X and Y represented in two’s complement format using 6 bits is:

The Boolean function Y=AB+CD is to be realized using only 2-input NAND gates. The minimum number of gates required is

The Boolean expression Y= $$\overline A \,\overline B \,\overline C \,D + \overline A BC\overline D + A\overline {B\,} \overline C \,D + AB\overline C \,\overline D $$

A new Binary Coded Pentary (BCP) number system is proposed in which every digit of a base-5 number is represented by its corresponding 3-bit binary code. For example, the base-5 nu...

Decimal 43 in Hexadecimal and BCD number system is respectively

The present output Q n of an edge triggered JK flip-flop is logic 0. If J=1, then Q n+1

The Boolean expression for the truth table shown is A B C D 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0

The minimum number of 2 to 1 multiplexers required to realize a 4 to 1 mutliplexer is

The range of signed decimal numbers that can be represented by 6-bite 1’s complement number is

11001, 1001 and 111001 correspond to the 2’s complement representation of which one of the following sets of number?

Choose the correct one from among the alternatives A, B, C, D after matching an item from Group 1 with the most appropriate item in Group 2. Group1 P. shift register Q. Counter R....

A master slave flip-flop has the characteristic that

The Boolean expression AC + B$$\overline C $$ is equivalent to

A Boolean function 'f' of two variables x and y is defined as follows: f(0,0)=f(0,1)=f(1,1)=1;f(1,0)=0 Assuming complements of x and y are not available, a minimum cost solution fo...

With out any additional circuitry, an 8:1 MUX can be used to obtain

If the functions W, X, Y and Z are as follows W= R+$$\overline P Q + \overline R $$ S X = $$X = PQ\overline R \,\overline S + \overline P \,\overline Q \,\overline R \,\overline S...

A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the syn...

The output of the 74 series of TTL gates is taken from a BJT in

The number of distinct Boolean expressions of 4 variables is

A 0 to 6 counter consist of 3 flip-flops and a combination circuit of 2 input gate(s). The combination circuit consists of

4-bit 2’s complement representation of a decimal number is 1000. The number is

The number of comparators required in a 3-bit comparator type ADC is

The 2’s complement representation of –17 is

The number of comparators in 4-bit flash ADC is

The Logical expression $$Y = A + \overline A B$$ is equivalent to

The circuit diagram of a synchronous counter is shown in the figure. Determine the sequence of states of the counter assuming that the initial state is ‘000’. Give your answer in a...

For a binary half-subtractor having two inputs A and B, the correct set of Logical expressions for the output D(=Aminus B) and X(=Borrow) are

For a binary half-sub-tractor having two inputs A and B, the correct set of logical expressions for the outputs D (=A minus B) and X (=borrow) are

In certain application, four inputs A, B, C, D (both true and complement forms available)are fed to logic circuit, producing an output F which operates a relay. The relay turns on...

The resolution of a 4-bit counting ADC is 0.5 Volts. For an analog input of 6.6 Volts, the digital output of the ADC will be

A Darlington Emitter follower circuit is sometimes used in the output stage of a TTL gate in order to

Commercially available ECL gates use two ground lines and one negative supply in order to

The minimized form of the logical expression ($$\overline A \,\overline B \,\overline C + B\overline C + \overline A B\overline C + \overline A BC + AB\overline C )$$

An equivalent 2’s complement representation of the 2’s complement number 1101 is

The advantage of using a dual slope ADC in a digital voltmeter is that

The noise margin of a TTL gate is about

For an ADC, match the following : if List 1 A. Flash converter B. Dual slope converter C. Successive approximation Converter List 2 1. requires a conversion time of the order of a...

Two 2' s complement numbers having sign bits x and y added and the sign bit of the result is z. Then, the occurrence of overflow is indicated by the Boolean function.

A signed integer has been stored in a byte using the 2's complement format. We wish to store the same integer in a 16-bit word. We should

In standard TTL the 'totem pole' stage refers to