GATE CSE & IT

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II: List-I List-II P. Immediate 1. Element of an array...

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destinatio...

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

The EX stage of a pipelined processor performs the memory read operations for LOAD instructions, and the operations for the arithmetic and logic instructions. Let $t_{E X}$ denote...

Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Servi...

A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance...

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three dif...

Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0 . The word with physical address...

The size of the physical address space of a processor is $2^{32}$ bytes. The capacity of a cache memory unit is $2^{23}$ bytes. The cache block size is 128 bytes. The cache memory...

Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words $\mathrm{P}, \mathrm{Q}, \mathrm{R...

Consider the real valued variables $X, Y$ and $Z$ represented using the IEEE 754 singleprecision floating-point format. The binary representations of $X$ and $Y$ in hexadecimal not...

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. T...

A disk of size 512 M bytes is divided into blocks of 64 K bytes. A file is stored in the disk using linked allocation. In linked allocation, each data block reserves 4 bytes to sto...

Consider a memory system with 1 M bytes of main memory and 16 K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 byt...

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store t...

A 5-stage instruction pipeline has stage delays of $180,250,150,170$, and 250 , respectively, in nanoseconds. The delay of an inter-stage latch is 10 nanoseconds. Assume that there...

An application executes $6.4 \times 10^8$ number of instructions in 6.3 seconds. There are four types of instructions, the details of which are given in the table. The duration of...

Which of the following is/are part of an Instruction Set Architecture of a processor?

Given a computing system with two levels of cache (L1 and L2) and a main memory. The first level (L1) cache access time is 1 nanosecond (ns) and the "hit rate" for L1 cache is $90...

For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no oth...

Which one of the following statements is FALSE?

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the fol...

Consider two set-associative cache memory architectures: WBC , which uses the write back policy, and WTC , which uses the write through policy. Both of them use the LRU ( Least Rec...

Consider a 512 GB hard disk with 32 storage surfaces. There are 4096 sectors per track and each sector holds 1024 bytes of data. The number of cylinders in the hard disk is ______

The baseline execution time of a program on a 2 GHz single core machine is 100 nanoseconds ( ns ). The code corresponding to 90% of the execution time can be fully parallelized. Th...

A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss rate on instruction cac...

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one o...

An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-1, source reg-2 Consider the following sequence of instructions to be exec...

A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand f...

A non-pipelined instruction execution unit operating at 2 GHz takes an average of 6 cycles to execute an instruction of a program P. The unit is then redesigned to operate on a 5-s...

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divid...

Consider a 3-stage pipelined processor having a delay of 10 ns (nanoseconds), 20 ns, and 14 ns, for the first, second, and the third stages, respectively. Assume that there is no o...

A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and cons...

An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK OFFSET. The number o...

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the...

A cache memory that has a hit rate of 0.8 has an access latency 10 ns and miss penalty 100 ns. An optimization is done on the cache to reduce the miss rate. However, the optimizati...

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execut...

A processor X 1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given prog...

Consider the following instruction sequence where register R1, R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X. Instruction Semantics Instr...

Consider a computer system with a byte-addressable primary memory of size 2 32 bytes. Assume the computer system has a direct-mapped cache of size 32 KB (1 KB = 2 10 bytes), and ea...

Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements. S 1 : Read misses in a write through L1 cache do not...

Consider a pipelined processor with 5 stages, Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, e...

If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices represent(s) the unsi...

A five-stage pipeline has stage delays of 150, 120, 150, 160 and 140 nanoseconds. The registers that are used between the pipeline stages have a delay of 5 nanoseconds each. The to...

Consider a set-associative cache of size 2 KB (1 KB = 2 10 bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32-bit address is used for acce...

Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals...

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, a...

Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overhea...

Consider the following statements. I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored interrupt, the CPU does polling to id...

A direct mapped cache memory of 1 MB has a block ize of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the firs...

A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider th...

A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How m...

A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a $60-\mathrm{MHz}$ clock. To service a cache...

The instruction pipeline of a $$RISC$$ processor has the following stages: Instruction Fetch $$(IF),$$ Instruction Decode $$(ID),$$ Operand Fetch $$(OF),$$ Perform Operation $$(PO)...

A $$32$$-bit wide main memory unit with a capacity of $$1$$ $$GB$$ is built using $$256M\,\, \times \,\,4$$-bit $$DRAM$$ chips. The number of rows of memory cells in the $$DRAM$$ c...

The size of the physical address space of a processor is $${2^P}$$ bytes. The word length is $${2^W}$$ bytes. The capacity of cache memory is $${2^N}$$ bytes. The size of each cach...

The following are some events that occur after a device controller issues an interrupt while process $$L$$ is under execution. $$(P)$$ The processor pushes the process status of $$...

Consider the following processor design characteristics. $$\,\,\,\,\,\,\,{\rm I}.\,\,\,\,\,$$ Register-to-register arithmetic operations only $$\,\,\,\,\,{\rm I}{\rm I}.\,\,\,\,\,$...

A processor has $$16$$ integer registers $$\left( {R0,\,\,R1,\,\,..\,\,,\,\,R15} \right)$$) and $$64$$ floating point registers $$(F0, F1,… , F63).$$ It uses a $$2$$-byte instructi...

Consider a $$3$$ $$GHz$$ (gigahertz) processor with a three-stage pipeline and stage latencies $${\tau _1},{\tau _2},$$ and $${\tau _3}$$ such that $${\tau _1} = 3{\tau _2}/4 = 2{\...

The stage delays in a $$4$$-stage pipeline are $$800, 500, 400$$ and $$300$$ picoseconds. The first stage (with delay $$800$$ picoseconds) is replaced with a functionally equivalen...

Consider a processor with $$64$$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one de...

The width of the physical address on a machine is $$40$$ bits. The width of the tag field in a $$512$$ $$KB$$ $$8$$-way set associative cache is _____________ bits.

Suppose the functions $$F$$ and $$G$$ can be computed in $$5$$ and $$3$$ nanoseconds by functional units $${U_F}$$ and $${U_G},$$ respectively. Given two instances of $${U_F}$$ and...

A processor has $$40$$ distinct instructions and $$24$$ general purpose registers. A $$32$$-bit instruction word has an opcode, two register operands and an immediate operand. The...

A processor can support a maximum memory of $$4$$ $$GB,$$ where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at le...

The size of the data count register of a $$DMA$$ controller is $$16$$ bits. The processor needs to transfer a file of $$29,154$$ kilobytes from disk to main memory. The memory is b...

Consider the sequence of machine instructions given below: MUL R5, R0, R1 DIV R6, R2, R3 ADD R7, R5, R6 SUB R8, R7, R4 In the above sequence, $$R0$$ to $$R8$$ are general purpose r...

Consider the following code sequence having five instructions $${I_1}$$ to $${I_5}$$. Each of these instructions has the following format. $$\,\,\,\,\,\,\,\,\,\,\,\,\,\,OP\,\,Ri,\,...

Consider a disk pack with a seek time of 4 milliseconds and rotational speed of 10000 rotations per minute (RPM). It has 600 sectors per track and each sector can store 512 bytes o...

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter $$(PC)$$ and Program Status Word $$(PSW),$$ are of size $$2$$ bytes. A stack...

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five...

Consider a machine with a byte addressable main memory of $${2^{20}}$$ bytes, block size of $$16$$ bytes and a direct mapped cache having $${2^{12}}$$ cache lines. Let the addresse...

Assume that for a certain processor, a read request takes $$50$$ nanoseconds on a cache miss and $$5$$ nanoseconds on a cache hit. Suppose while running a program, it was observed...

Consider a typical disk that rotates at $$15000$$ rotations per minute $$(RPM)$$ and has a transfer rate of $$50 \times {10^6}\,\,\,bytes/\sec .$$ If the average seek time of the d...

For computers based on three-address instruction formats, each address field can be used to specify which of the following: (S1) A memory operand (S2) A processor register (S3) An...

Consider two processors ܲ$${P_1}$$ and $${P_2}$$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $${P_2}$$ take...

In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?

An instruction pipeline has five stages, namely, instruction fetch $$(IF),$$ instruction decode and register fetch $$(ID/RF)$$ instruction execution $$(EX),$$ memory access $$(MEM)...