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GATE Electrical Engineering · Digital Circuits - Counters/Frequency Dividers · 2018-2023

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2023 Q56

Neglecting the delays due to the logic gates in the circuit shown in figure, the decimal equivalent of the binary sequence [ABCD] of initial logic states, which will not change wit...

medium
2018 Q36

Which one of the following statements is true about the digital circuit shown in the figure

mediumanswer key
2018 Q49

For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions Q_A Q_B Q_C = Q'_A Q'_B Q'_C = 100. The minimum number of clock cycles after whi...

hardanswer key