Digital Electronics - CMOS Inverter
GATE Electronics & Communication · 2 questions across 1 years (2019-2019) · 3% recurrence rate
Recurrence sparkline
2019–201920192019
Difficulty mix
med 100%
Question types
MCQ1
NAT1
All 2 questions on Digital Electronics - CMOS Inverter
2019 Q13
A standard CMOS inverter is designed with equal rise and fall times ($\beta_n = \beta_p$). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin ($NM_L$) and t...
Med
2019 Q53
A CMOS inverter, designed to have a mid-point voltage V_I equal to half of Vdd, as shown in the figure, has the following parameters: Vdd = 3 V μn Cox = 100 μA/V^2 ; Vtn = 0.7 V for nMOS μp Cox = 40 μA/V^2 ; |Vtp| = 0.9...
Med📊