propagation delay

In the circuit shown below, the AND gate has a propagation delay of 1 ns. The edge-triggered flip-flops have a set-up time of 2 ns, a hold-time of 0 ns, and a clock-to-Q delay of 2...

The propagation delay of the 2×1 MUX shown in the circuit is 10 ns. Consider the propagation delay of the inverter as 0 ns. If S is set to 1 then the output Y is _________.

For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is ________ (rounded off to the nearest integer).

The phase response of a passband waveform at receiver is given by $$\varphi \,(f) = - 2\,\pi \,\alpha \,(f - {f_c}) - \,2\pi \beta \,{f_c}$$ where $${f_c}$$ is the centre frequency...

A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the syn...

A ring oscillator consisting of 5 inverters is running at a frequency of 1.0 MH$$_z$$. The progagation delay per gate is ______

Synchronous counters are _____ than the ripple counters.

A pulse train with a frequency of 1 MHz is counted using a modulo-1024 ripple-counter built with J-K flip flops. For proper operation of the counter, the maximum permissible propag...

A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 50ns, the maximum clock frequency that can be used is equal to:

Among the digital IC-families-ECL, TTL and CMOS: