NAND gate

For the circuit shown below, the propagation delay of each NAND gate is 1 ns. The critical path delay, in ns, is ________ (rounded off to the nearest integer).

The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is

The minimum number of NAND gates required to implement the Boolean function $$A + A\overline B $$ $$ + A\overline B C$$ is equal to

Implement the function $$F=\left(\overline A+\overline B\right)\left(\overline C+\overline D\right)$$ using two open collector TTL 2-input NAND gates.