Concept drill
JK flip-flop
GATE Electronics & Communication · Digital Electronics - Flip-Flops · 1999-2026
3
PYQs
67%
keyed
0
elite explanations
3
years appeared
Study anchor
Source-book anchor pending for this concept.
Practice action
Start latest PYQPYQs in this concept
All concepts →2026 Q35
The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of 10 cycles/second is applied to its clock (C) input. The frequency...
mediumanswer key
2005 PYQ
The present output Q n of an edge triggered JK flip-flop is logic 0. If J=1, then Q n+1
easyanswer key
1999 PYQ
The circuit diagram of a synchronous counter is shown in the figure. Determine the sequence of states of the counter assuming that the initial state is ‘000’. Give your answer in a...
medium