digital electronics

A binary ripple counter is designed to count (0)10 to (64)10. Which of the following is/are the number of flip-flops required to design the counter?

The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of 10 cycles/second is applied to its clock (C) input. The frequency...

What is the 10's complement of (47)10?

For the Boolean function F(A, B, C, D) = ∑m(0,2,5,7,8,10,12,13,14,15), the essential prime implicants are ____________.

The sequence of states (Q1Q0) of the given synchronous sequential circuit is

The synchronous sequential circuit shown below works at a clock frequency of 1 GHz. The throughput, in Mbits/s, and the latency, in ns, respectively, are

The signal-to-noise ratio (SNR) of an ADC with a full-scale sinusoidal input is given to be 61.96 dB. The resolution of the ADC is _________ bits (rounded off to the nearest intege...

In a given sequential circuit, initial states are Q1 = 1 and Q2 = 0. For a clock frequency of 1 MHz, the frequency of signal Q2 in kHz, is ________ (rounded off to the nearest inte...