Memory Management

A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB . TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entries. The paging system uses pages of size...

Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is...

Consider contiguous allocation of physical memory to processes using variable partitioning scheme. Suppose there are 8 holes in the memory of sizes $20 \mathrm{~KB}, 4 \mathrm{~KB}$, $25 \mathrm{~KB}, 18 \mathrm{~KB}, 7...

Consider a demand paging memory management system with 32-bit logical address, 20 -bit physical address, and page size of 2048 bytes. Assuming that the memory is byte addressable, what is the maximum number of entries in...

A computer system supports a logical address space of 232 bytes. It uses two-level hierarchical paging with a page size of 4096 bytes. A logical address is divided into a b-bit index to the outer page table, an offset wi...

Consider a memory management system that uses a page size of 2 KB. Assume that both the physical and virtual addresses start from 0. Assume that the pages 0, 1, 2, and 3 are stored in the page frames 1, 3, 2, and 0, resp...

Consider a 32-bit system with 4 KB page size and page table entries of size 4 bytes each. Assume 1 KB = $2^{10}$ bytes. The OS uses a 2-level page table for memory management, with the page table containing an outer page...

Which of the following tasks is/are the responsibility/responsibilities of the memory management unit (MMU) in a system with paging-based memory management?

Consider a computer system with 57-bit virtual addressing using multi-level tree-structured page tables with L levels for virtual to physical address translation. The page size is 4 KB (1 KB = 1024 B) and a page table en...

Which one of the following statements is FALSE?

In the context operating systems, which of the following statements is/are correct with respect to paging?

Consider allocation of memory to a new process. Assume that none of the existing holes in the memory will exactly fit the process's memory requirement. Hence, a new hole of smaller size will be created if allocation is m...

Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8 kB and the word size is 4 bytes. The Translation L...

Consider a computer system with $$40$$-bit virtual addressing and page size of sixteen kilobytes. If the computer system has a one-level page table per process and each page table entry requires $$48$$ bits, then the siz...

Consider a system with byte-addressable memory, 32-bit logical addresses, 4 kilobyte page size and page table entries of 4 bytes each. The size of the page table in the system in megabytes is ________.

A computer system implements $$8$$ kilobyte pages and a $$32$$-bit physical address space. Each page table entry contains a valid bit, a dirty bit, three permission bits, and the translation. If the maximum size of the p...

Consider six memory partitions of sizes $$200$$ $$KB,$$ $$400$$ $$KB,$$ $$600$$ $$KB,$$ $$500$$ $$KB,$$ $$300$$ $$KB$$ and $$250$$ $$KB,$$ where $$KB$$ refers to kilobyte. These partitions need to be allotted to four pro...

A computer system implements a $$40$$-bit virtual address, page size of $$8$$ kilobytes, and a $$128$$-entry translation look-aside buffer $$(TLB)$$ organized into $$32$$ sets each having four ways. Assume that the $$TLB...

Consider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory. It takes 10 milliseconds to search the TLB and 80 milliseconds to access the physical memory. If the...

The essential content(s) in each entry of a page table is / are:

A multilevel page table is preferred in comparison to a single level page table for translating virtual address to physical address because.

A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address tran...

What is the swap space in the disk used for?

Which of the following addressing modes are suitable for program relocation at run time? $$1.$$ Absolute addressing $$2.$$ Based addressing $$3.$$ Relative addressing $$4.$$ Indirect addressing

Consider a program $$P$$ that consists of two source modules $${M_1}$$ and $${M_2}$$ contained in two different files. If $${M_1}$$ contains a reference to a function defined in $${M_2}$$, the reference will be resolved...

A processor uses $$2$$-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $$32$$ bits wide. The memory is byt...

A processor uses $$2$$-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $$32$$ bits wide. The memory is byt...

In a system with $$32$$ bit virtual addresses and $$1$$ $$KB$$ page size, use of one-level page tables for virtual to physical address translation is not practical because of

A computer system uses $$32$$-bit virtual address, and $$32$$-bit physical address. The physical memory is byte addressable, and the page size is $$4$$ kbytes. It is decided to use two level page tables to translate from...

Where does the swap space reside?

Consider a machine with 64 MB physical memory and a 32-bit virtual address space. If the page size is 4KB, what is the approximate size of the page table?

The process of assigning load addresses to the various parts of the program and adjusting the code and date in the program to reflect the assigned addresses is called

A certain computer system has the segmented paging architecture for virtual memory. The memory is byte addressable. Both virtual and physical address spaces contain $${2^{16}}$$ bytes each. The virtual address space is d...

In a resident $$–OS$$ computer, which of the following systems must reside in the main memory under all situations?

A $$1000$$ Kbyte memory is managed using variable partitions but to compaction. It currently has two partitions of sizes $$200$$ Kbytes and $$260$$ Kbytes respectively. The smallest allocation request in Kbytes that coul...

A linker is given object modules for a set of programs that were compiled separately. What information need to be included in an object module?

The principle of locality justifies the use of

A computer installation has 1000K of main memory. The jobs arrive and finish in the following sequence. Job 1 requiring 200k arrives Job 2 requiring 350k arrives Job 3 requiring 300k arrives Job 1 finishes Job 4 requirin...

In a paged segmented scheme of memory management, the segment table itself must have a page table because:

A ''link editor'' is a program that:

State whether the following statement TRUE or FALSE. The best-fit techniques for memory allocation ensures the memory will never be fragmented.

State whether the following statements are TRUE or FALSE with reason. The Link-load -and-go loading scheme required less storange space than the Link-and-go loading scheme.

Under paged memory management scheme simple lock and key memory protection arrangement may still be required if the $$........$$ processors do not have address mapping hardware.