Instruction Set Architecture

Consider a processor that has 16 general purpose registers and it uses 2-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-...

Match each addressing mode in List I with a data element or an element of a data structure (in a high-level language) in List II: List-I List-II P. Immediate 1. Element of an array Q. Indirect 2. Pointer R. Base with ind...

Consider a processor P whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand. Which one of the following se...

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instr...

Which of the following is/are part of an Instruction Set Architecture of a processor?

A processor uses a 32-bit instruction format and supports byte-addressable memory access. The ISA of the processor has 150 distinct instructions. The instructions are equally divided into two types, namely R-type and I-t...

A processor with 16 general purpose registers uses a 32-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a 16-bit scalar field. If 8 a...

Consider the following instruction sequence where register R1, R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X. Instruction Semantics Instruction Size (bytes) MOV R1, (5000) R1 ←...

A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type...

A processor has $$16$$ integer registers $$\left( {R0,\,\,R1,\,\,..\,\,,\,\,R15} \right)$$) and $$64$$ floating point registers $$(F0, F1,… , F63).$$ It uses a $$2$$-byte instruction format. There are four categories of...

Consider the following processor design characteristics. $$\,\,\,\,\,\,\,{\rm I}.\,\,\,\,\,$$ Register-to-register arithmetic operations only $$\,\,\,\,\,{\rm I}{\rm I}.\,\,\,\,\,$$ Fixed-length instruction format $$\,\,...

A processor has $$40$$ distinct instructions and $$24$$ general purpose registers. A $$32$$-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immedia...

Consider a processor with $$64$$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a twe...

For computers based on three-address instruction formats, each address field can be used to specify which of the following: (S1) A memory operand (S2) A processor register (S3) An implied accumulator register

Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter $$(PC)$$ and Program Status Word $$(PSW),$$ are of size $$2$$ bytes. A stack in the main memory is implemented from...

A machine has a $$32$$-bit architecture, with $$1$$-word long instructions. It has $$64$$ registers, each of which is $$32$$ bits long. It needs to support $$45$$ instructions, which have an immediate operand in addition...

Consider a hypothetical processor with an instruction of type $$LW$$ $$R1, 20(R2),$$ which during execution reads a $$32$$-bit word from memory and stores it in a $$32$$-bit register $$R1.$$ The effective address of the...

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for $$1.\,\,\,\,$$ Function locals and parameters $$2.\,\,\,\,$$ Register saves and restores $$3.\,\,\,\,$$ Instructio...

Which of the following is/are true of the auto increment addressing mode? $$1.$$ It is useful in creating self relocating code $$2.$$ If it is included in an Instruction Set Architecture, then an additional $$ALU$$ is re...

A $$CPU$$ has $$24$$-bit instructions. A program starts at address $$300$$ (in decimal). Which one of the following is a legal program counter (all values in decimal)?

Consider a three word machine instruction $$ADD$$ $$A$$ $$\left[ {{R_0}} \right],\,@\,B$$ The first operand (destination) ''$$A$$ $$\left[ {{R_0}} \right]''$$ uses indexed addressing mode with $${{R_0}}$$ as the index re...

Which of the following addressing modes are suitable for program relocation at run time? $$1.$$ Absolute addressing $$2.$$ Based addressing $$3.$$ Relative addressing $$4.$$ Indirect addressing

Which of the following is not a form of memory?

Which of the following is not a form of memory?

Which is the most appropriate match for the items in the first column with the items in the second column? $$X.$$ Indirect Addressing $$Y.$$ Indexed Addressing $$Z.$$ Base Register Addressing $${\rm I}.\,\,$$Array implem...

Suppose a processor does not have any stack pointer register. Which of the following statements is true?

The most appropriate matching for the following pairs $$X:$$ Indirect addressing $$Y:$$ Immediate addressing $$Z:$$ Auto decrement addressing is $$1:$$ Loops $$2:$$ Pointers $$3.$$ Constants

A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor?

The main difference (s) between a $$CISC$$ and a $$RISC$$ processor is/are that a $$RISC$$ processor typically:

What are x and y in the following macro definition? macro Add x,y Load y Mul x Store y end macro