I/O & Buses

Consider the following two statements about interrupt handling mechanisms in a CPU. S1: In non-vectored interrupt mechanism, it usually takes more time to start the Interrupt Service Routine (ISR) when compared to that i...

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interr...

Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rat...

Which one of the following statements is FALSE?

A keyboard connected to a computer is used at a rate of 1 keystroke per second. The computer system polls the keyboard every 10 ms (milli seconds) to check for a keystroke and consumes 100 $$\mu$$s (micro seconds) for ea...

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% pr...

Consider the following statements. I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored interrupt, the CPU does polling to identify the source of the interrupt. III....

The following are some events that occur after a device controller issues an interrupt while process $$L$$ is under execution. $$(P)$$ The processor pushes the process status of $$L$$ onto the control stack. $$(Q)$$ The...

The size of the data count register of a $$DMA$$ controller is $$16$$ bits. The processor needs to transfer a file of $$29,154$$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of t...

Consider a typical disk that rotates at $$15000$$ rotations per minute $$(RPM)$$ and has a transfer rate of $$50 \times {10^6}\,\,\,bytes/\sec .$$ If the average seek time of the disk is twice the average rotational dela...

Consider a disk pack with a seek time of 4 milliseconds and rotational speed of 10000 rotations per minute (RPM). It has 600 sectors per track and each sector can store 512 bytes of data. Consider a file stored in the di...

Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $$100$$ nanoseconds ($$ns$$) by the data, address,...

A computer handles several interrupt sources of which of the following are relevant for this question. $$ * \,\,\,\,\,\,\,\,\,\,\,$$ Interrupt from $$CPU$$ temperature sensor (raises interrupt if $$CPU$$ $$\,\,\,\,\,\,\,...

On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer $$500$$ bytes from an $${\rm I}/O$$ device to memory. Initialize the address register Ini...

On a non-pipe-lined sequential processor, a program segment, which is a part of the interrrupt service routine, is given to transfer $$500$$ bytes from an $${\rm I}/O$$ device to memory. Initialize the address register I...

A $$CPU$$ generally handles an interrupt by executing an interrupt service routine

Which of the following must be true for the $$RFE$$ (Return From Exception) instruction on a general purpose processor? $$1.$$ It must be a trap instruction $$2.$$ It must be a privileged instruction $$3.$$ An exception...

Normally user programs are prevented from handling $${\rm I}/O$$ directly by $${\rm I}/O$$ instructions in them. For $$CPUs$$ having explicit $${\rm I}/O$$ instructions, such $${\rm I}/O$$ protection is ensured by having...

A device with data transfer rate $$10$$ $$KB/sec$$ is connected to a $$CPU.$$ Data is transferred byte-wise. Let the interrupt overhead be $$4$$ $$\mu \sec $$. The byte transfer time between the device interface register...

Consider the disk drive with the following specifications $$16$$ surfaces, $$512$$ tracks/surface, $$512$$ sectors/track, $$1$$ $$KB/sector$$, rotation speed $$3000$$ $$rpm.$$ The disk is operated in cycle stealing mode...

Which one of the following is true for a $$CPU$$ having a single interrupt request line and single interrupt grant line?

How many $$8$$-bit characters can be transmitted per second over $$9600$$ baud serial communication link using a parity synchronous mode of transmission with one start bit & Eight data bits, two stop bits, and one parity...

A Hard disk with a transfer rate of $$10Mbytes/second$$ is constantly transferring data to memory using $$DMA.$$ The processor runs at $$600MHz$$ and takes $$300$$ and $$900$$ clock cycles to initiate and complete $$DMA$...

In serial data transmission, every byte of data is padded with a $$‘0’$$ in the beginning and one or two $$‘1’s$$ at the end of byte because

A processor needs software interrupt to

Which of the following device should get higher priority on assigning interrupts?

Which of the following is true?

The correct matching for the following pairs is $$\,\,\,\,\,$$ List - $${\rm I}$$ (a) $$DMA$$ $$\,\,$$ $${\rm I}/O$$ (b) Cache (c) Interrupt $${\rm I}/O$$ (d) Condition Code Register $$\,\,\,\,\,$$ List - $${\rm II}$$ (1...

It gives non-uniform priority to various devices.

Start and stop bits do not contain 'information' but these are used in serial communication for