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Concept drill

write policies

GATE CSE & IT · Memory Hierarchy & Cache · 2021-2022

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Morris Mano / Patterson-Hennessy

Digital logic, datapath, memory hierarchy, instruction sets

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2022 PYQ

Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the...

mediumanswer keybasic explanation
2021 PYQ

Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements. S 1 : Read misses in a write through L1 cache do not...

mediumanswer keybasic explanation