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GATE CSE & IT · Memory Hierarchy & Cache · 2007-2007

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Morris Mano / Patterson-Hennessy

Digital logic, datapath, memory hierarchy, instruction sets

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2007 PYQ

Consider a $$4$$-way set associative cache consisting of $$128$$ lines with a line size of $$64$$ words. The $$CPU$$ generates a $$20$$-bit address of a word in main memory. The nu...

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