Concept drill
memory-organization
GATE CSE & IT · Memory Hierarchy & Cache · 2009-2018
4
PYQs
75%
keyed
0
elite explanations
3
years appeared
Study anchor
Morris Mano / Patterson-Hennessy
Digital logic, datapath, memory hierarchy, instruction sets
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All concepts →2018 PYQ
A $$32$$-bit wide main memory unit with a capacity of $$1$$ $$GB$$ is built using $$256M\,\, \times \,\,4$$-bit $$DRAM$$ chips. The number of rows of memory cells in the $$DRAM$$ c...
medium
2010 PYQ
A main memory unit with a capacity of $$4$$ megabytes is built using $$1M \times 1$$-bit $$DRAM$$ chips. Each $$DRAM$$ chip has $$1K$$ rows of cells with $$1K$$ cells in each row....
mediumanswer key
2009 PYQ
How many $$32K\,\, \times \,\,1RAM$$ chips are needed to provide a memory capacity of $$256$$ $$K$$-bytes?
easyanswer key
2009 PYQ
How many $$32k$$ x $$1$$ $$RAM$$ chips are needed to provide a memory capacity of $$256$$ $$K$$-bytes?
easyanswer key