memory hierarchy

A computer has a memory hierarchy consisting of two-level cache (L1 and L2) and a main memory. If the processor needs to access data from memory, it first looks into L1 cache. If t...

For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no oth...

An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK OFFSET. The number o...

Consider a set-associative cache of size 2 KB (1 KB = 2 10 bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32-bit address is used for acce...

The read access times and the hit ratios for different caches in a memory hierarchy are as given below. Cache | Read access time (in nanoseconds) | Hit ratio ---|---|--- I-cache |...

In a $$k$$-way set associative cache, the cache is divided into $$v$$ sets, each of which consists of $$k$$ lines. The lines of a set are placed in sequence one after another. The...

A computer has a $$256$$ $$K$$ Byte, $$4$$-way set associative, write back data cache with block size of $$32$$ Bytes. The processor sends $$32$$ bit addresses to the cache control...

The principle of locality justifies the use of