Concept drill
memory bandwidth
GATE CSE & IT · I/O & Buses · 2014-2019
2
PYQs
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keyed
0
elite explanations
2
years appeared
Study anchor
Morris Mano / Patterson-Hennessy
Digital logic, datapath, memory hierarchy, instruction sets
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A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a $60-\mathrm{MHz}$ clock. To service a cache...
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2014 PYQ
Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $$100$$ na...
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