Concept drill
interleaved memory
GATE CSE & IT · I/O & Buses · 1990-2014
2
PYQs
50%
keyed
0
elite explanations
2
years appeared
Study anchor
Morris Mano / Patterson-Hennessy
Digital logic, datapath, memory hierarchy, instruction sets
Practice action
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Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $$100$$ na...
medium
1990 PYQ
State whether the following statements are TRUE or FALSE with reason. Transferring data in blocks from the main memory to the cache memory enables an interleaved main memory unit t...
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