Concept drill
Flip-flops
GATE CSE & IT · Digital Logic - Counters and Flip-flops · 2015-2017
3
PYQs
67%
keyed
0
elite explanations
3
years appeared
Study anchor
Source-book anchor pending for this concept.
Practice action
Start latest PYQPYQs in this concept
All concepts →2017 Q42
The next state table of a 2-bit saturating up-counter is given below. Q1 Q0 | Q1+ Q0+ 0 0 | 0 1 0 1 | 1 0 1 0 | 1 1 1 1 | 1 1 The counter is built as a synchronous sequential circu...
mediumanswer key
2016 PYQ
We want to design a synchronous counter that counts the sequence $$0-1-0-2-0-3$$ and then repeats. The minimum number of $$J-K$$ flip-flops required to implement this counter is __...
medium
2015 PYQ
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of...
mediumanswer key