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Digital Logic

GATE CSE & IT · Digital Logic - Multiplexers · 1996-2026

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2026 PYQ

Which one of the following options is not a property of Boolean Algebra? Note: + is OR operation, • is AND operation, and ' is NOT operation

easyanswer keybasic explanation
2026 PYQ

Consider a 2-bit saturating up/down counter that performs the saturating up count when the input $P$ is 0 , and the saturating down count when $P$ is 1 . The Next State table of th...

mediumanswer keybasic explanation
2025 Q24

Let X be a 3-variable Boolean function that produces output as '1' when at least two of the input variables are '1'. Which of the following statement(s) is/are CORRECT, where a, b,...

mediumanswer key
2025 Q25

The number -6 can be represented as 1010 in 4-bit 2's complement representation. Which of the following is/are CORRECT 2's complement representation(s) of -6?

mediumanswer key
2025 Q42

Consider the following four variable Boolean function in sum-of-product form $F(b_3, b_2, b_1, b_0) = \Sigma(0, 2, 4, 8, 10, 11, 12)$. where the value of the function is computed b...

mediumanswer key
2025 Q43

Given the following Karnaugh Map for a Boolean function F(w,x, y, z): Which one or more of the following Boolean expression(s) represent(s) F?

mediumanswer key
2025 Q50

Which of the following Boolean algebraic equation(s) is/are CORRECT?

mediumanswer key
2025 Q59

Consider a finite state machine (FSM) with one input X and one output f, represented by the given state transition table. The minimum number of states required to realize this FSM...

mediumanswer key
2024 Q28

Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the f...

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2024 Q30

For a Boolean variable x, which of the following statements is/are FALSE?

easyanswer key
2024 Q50

Consider 4-variable functions f1, f2, f3, f4 expressed in sum-of-minterms form as given below. f1 = ∑(0,2,3,5,7,8,11,13) f2 = ∑(1,3,5,7,11,13, 15) f3 = ∑(0,1,4,11) f4 = ∑(0,2,6,13)...

mediumanswer key
2024 Q64

Consider a digital logic circuit consisting of three 2-to-1 multiplexers M1, M2, and M3 as shown below. X1 and X2 are inputs of M1. X3 and X4 are inputs of M2. A, B, and C are sele...

mediumanswer key
2017 Q42

The next state table of a 2-bit saturating up-counter is given below. Q1 Q0 | Q1+ Q0+ 0 0 | 0 1 0 1 | 1 0 1 0 | 1 1 1 1 | 1 1 The counter is built as a synchronous sequential circu...

mediumanswer key
2006 PYQ

Given two three bit number $${a_2}{a_1}{a_0}$$ and $${b_2}{b_1}{b_0}$$ and $$c,$$ the carry in the function that represents the carry generate function when these two numbers are a...

mediumanswer key
2004 PYQ

$$A$$ $$4$$-bit carry look ahead adder, which adds two $$4$$-bit numbers, is designed using $$AND,$$ $$OR,$$ $$NOT,$$ $$NAND,$$ $$NOR$$ gates only. Assuming that all the inputs are...

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1999 PYQ

The maximum gate delay for any output to appear in an array multiplier for multiplying two n bit number is

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1999 PYQ

The number of full and half-adders required to add 16-bit numbers is:

easyanswer key
1996 PYQ

A ROM is sued to store the table for multiplication of two $$8$$-bit unsigned integers. The size of ROM required is

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