Concept drill
data-bus
GATE CSE & IT · Memory Hierarchy & Cache · 1995-2014
2
PYQs
100%
keyed
0
elite explanations
2
years appeared
Study anchor
Morris Mano / Patterson-Hennessy
Digital logic, datapath, memory hierarchy, instruction sets
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All concepts →2014 PYQ
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
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1995 PYQ
The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate address and data lines are needed for a memory of $$4K\,\,...
easyanswer key