Concept drill
clock-frequency
GATE CSE & IT · Datapath & Control · 2014-2026
3
PYQs
33%
keyed
0
elite explanations
2
years appeared
Study anchor
Morris Mano / Patterson-Hennessy
Digital logic, datapath, memory hierarchy, instruction sets
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A non-pipelined instruction execution unit that operates at 1.6 GHz clock takes an average of 5 clock cycles to complete the execution of an instruction. To improve the performance...
mediumbasic explanation
2014 PYQ
Consider two processors ܲ$${P_1}$$ and $${P_2}$$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $${P_2}$$ take...
easy
2014 PYQ
Consider the following processors ($$ns$$ stands for nanoseconds). Assume that the pipeline registers have zero latency. $$P1:$$ Four-stage pipeline with stage latencies $$1$$ $$ns...
easyanswer key