Concept drill
cache-size
GATE CSE & IT · Memory Hierarchy & Cache · 2008-2025
2
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2
years appeared
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Morris Mano / Patterson-Hennessy
Digital logic, datapath, memory hierarchy, instruction sets
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All concepts →2025 PYQ
For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no oth...
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2008 PYQ
For inclusion to hold between two cache levels $$L1$$ and $$L2$$ in a multilevel cache hierarchy, which of the following are necessary? $$1.$$ $$L1$$ must be a write-through cache...
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