Skip to content
Early access — you're among the first to try PYQLabs. Share feedback
Concept drill

bus timing

GATE CSE & IT · I/O & Buses · 2014-2014

1
PYQs
0%
keyed
0
elite explanations
1
years appeared

Study anchor

Morris Mano / Patterson-Hennessy

Digital logic, datapath, memory hierarchy, instruction sets

Practice action

Start latest PYQ

PYQs in this concept

All concepts →
2014 PYQ

Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $$100$$ na...

medium