Concept drill
branch prediction
GATE CSE & IT · Pipelining · 2008-2022
2
PYQs
50%
keyed
0
elite explanations
2
years appeared
Study anchor
Morris Mano / Patterson-Hennessy
Digital logic, datapath, memory hierarchy, instruction sets
Practice action
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All concepts →2022 PYQ
A processor X 1 operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given prog...
mediumbasic explanation
2008 PYQ
Which of the following are NOT true in a pipelined processor? $$1.$$ Bypassing can handle all RAW hazards $$2.$$ Register renaming can eliminate all register carried WAR hazards $$...
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