address translation

A system has a Translation Lookaside Buffer (TLB) that has a reach of 1 MB . TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entrie...

Consider a computer system with 57-bit virtual addressing using multi-level tree-structured page tables with L levels for virtual to physical address translation. The page size is...

Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8 kB and the...

A Computer system supports $$32$$-bit virtual addresses as well as $$32$$-bit physical addresses. Since the virtual address space is of the same size as the physical address space,...

A processor uses $$2$$-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are...

A computer system uses $$32$$-bit virtual address, and $$32$$-bit physical address. The physical memory is byte addressable, and the page size is $$4$$ kbytes. It is decided to use...